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1 september 2003 dsc-4667/12 ? 2003 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. 3.3v high-density supersync? ii 36-bit fifo 1,024 x 36, 2,048 x 36 4,096 x 36, 8,192 x 36 16,384 x 36, 32,768 x 36 idt72v3640, idt72v3650 idt72v3660, idt72v3670 idt72v3680, idt72v3690 idt and the idt logo are a registered trademarks of integrated device technology, inc. the supersync ii fifo is a trademark of integrated device technology, inc. commercial and industrial temperature ranges features: ? ? ? ? ? choose among the following memory organizations: commercial idt72v3640 ? ? ? ? ? 1,024 x 36 idt72v3650 ? ? ? ? ? 2,048 x 36 idt72v3660 ? ? ? ? ? 4,096 x 36 idt72v3670 ? ? ? ? ? 8,192 x 36 idt72v3680 ? ? ? ? ? 16,384 x 36 idt72v3690 ? ? ? ? ? 32,768 x 36 ? ? ? ? ? up to 166 mhz operation of the clocks ? ? ? ? ? user selectable asynchronous read and/or write ports (pbga only) ? ? ? ? ? user selectable input and output port bus-sizing - x36 in to x36 out - x36 in to x18 out - x36 in to x9 out - x18 in to x36 out - x9 in to x36 out ? ? ? ? ? pin to pin compatible to the higher density of idt72v36100 and idt72v36110 ? ? ? ? ? big-endian/little-endian user selectable byte representation ? ? ? ? ? 5v input tolerant ? ? ? ? ? fixed, low first word latency ? ? ? ? ? zero latency retransmit ? ? ? ? ? auto power down minimizes standby power consumption ? ? ? ? ? master reset clears entire fifo ? ? ? ? ? partial reset clears data, but retains programmable settings ? ? ? ? ? empty, full and half-full flags signal fifo status ? ? ? ? ? programmable almost-empty and almost-full flags, each flag can default to one of eight preselected offsets ? ? ? ? ? selectable synchronous/asynchronous timing modes for almost- empty and almost-full flags ? ? ? ? ? program programmable flags by either serial or parallel means ? ? ? ? ? select idt standard timing (using ef and ff flags) or first word fall through timing (using or and ir flags) ? ? ? ? ? output enable puts data outputs into high impedance state ? ? ? ? ? easily expandable in depth and width ? ? ? ? ? jtag port, provided for boundary scan function (pbga only) ? ? ? ? ? independent read and write clocks (permit reading and writing simultaneously) ? ? ? ? ? available in a 128-pin thin quad flat pack (tqfp) or a 144-pin plastic ball grid array (pbga) (with additional features) ? ? ? ? ? high-performance submicron cmos technology ? ? ? ? ? industrial temperature range (?40 c to +85 c) is available functional block diagram input register output register ram array 1,024 x 36, 2,048 x 36 4,096 x 36, 8,192 x 36 16,384 x 36, 32,768 x 36 flag logic ff / ir paf ef / or pae hf read pointer read control logic write control logic write pointer reset logic wen wclk/wr d 0 -d n (x36, x18 or x9) ld mrs ren rclk/rd oe q 0 -q n (x36, x18 or x9) offset register prs fwft/si sen rt 4667 drw01 bus configuration bm control logic be ow ip pfm fsel0 fsel1 iw rm asyr asyw jtag control (boundary scan) tck tms tdo tdi trst * * * * * * * * * * *available on the pbga package only.
2 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 pin configurations tqfp (pk128-1, order code: pf) top view description: the idt72v3640/72v3650/72v3660/72v3670/72v3680/72v3690 are exceptionally deep, high speed, cmos first-in-first-out (fifo) memories with clocked read and write controls and a flexible bus-matching x36/x18/x9 data flow. these fifos offer several key user benefits: ? flexible x36/x18/x9 bus-matching on both read and write ports the period required by the retransmit operation is fixed and short. the first word data latency period, from the time the first word is written to an empty fifo to the time it can be read, is fixed and short. asynchronous/synchronous translation on the read or write ports high density offerings up to 1 mbit bus-matching sync fifos are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. each fifo has a data input port (d n ) and a data output port (q n ), both of which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the state of external control pins input width (iw), output width (ow), and bus- matching (bm) pin during the master reset cycle. the input port can be selected as either a synchronous (clocked) interface, or asynchronous interface. during synchronous operation the input port is controlled by a write clock (wclk) input and a write enable ( wen ) input. data present on the dn data inputs is written into the fifo on every rising edge of note: 1. dnc = do not connect. v cc oe 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 iw d35 d34 d33 d32 d31 v cc d30 gnd d29 d28 d27 d26 d25 d24 d23 gnd d22 d21 d20 d19 d18 gnd d17 d16 d15 v cc d13 d12 gnd d11 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 102 101 q35 q34 q33 q32 gnd gnd q31 q30 q29 q28 q27 q26 q25 q24 gnd gnd q23 q22 q21 q20 q19 q18 gnd q17 q16 q15 q14 q13 q12 gnd q11 q10 index wen sen dnc (1) d14 v cc v cc v cc v cc v cc v cc 4667 drw02a dnc (1) rt ren rclk pae pfm ef / or rm gnd v cc bm ip be fs1 gnd hf fs0 ow gnd paf v cc ff / ir fwft/si ld mrs prs wclk 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 d10 d9 d8 d7 d6 gnd d5 d4 d2 d1 d0 gnd q0 q1 q2 q3 q4 q5 gnd q6 q7 q9 104 103 q8 v cc v cc d3
3 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 pin configurations (continued) pbga: 1mm pitch, 13mm x 13mm (bb144-1, order code: bb) top view asyw wen wclk paf ff / ir hf bm ef rclk ren oe q35 sen iw prs ld mrs fs0 fs1 asyr ip pfm rt q34 d35 d34 d33 fwft/si ow v cc v cc be pae rm q32 q3 3 d32 d31 d30 v cc v cc gnd gnd v cc v cc q29 q30 q31 d29 d26 d27 v cc q26 q27 q28 d28 d25 d24 q23 q24 q25 d21 d22 d23 q22 q21 q20 d18 d19 d20 v cc q19 q18 q17 d15 d16 d17 v cc q16 q15 q14 d12 d13 d14 d3 d0 v cc v cc tdo q2 q13 q12 q11 d10 d6 d4 d1 tms tck q0 q3 q5 q10 q9 d8 d7 d5 d2 trst tdi q1 q4 q6 q7 q8 a1 ball pad corner a b c d e f g h j k l m 12 3 4 5 6 7 8 9 1011 12 4667 drw02b gnd gnd gnd gnd gnd gnd gnd gnd v cc gnd gnd gnd gnd v cc gnd gnd v cc v cc gnd gnd gnd gnd d11 d9 v cc v cc v cc v cc v cc wclk when wen is asserted. during asynchronous operation only the wr input is used to write data into the fifo. data is written on a rising edge of wr, the wen input should be tied to its active state, (low). the output port can be selected as either a synchronous (clocked) interface, or asynchronous interface. during synchronous operation the output port is controlled by a read clock (rclk) input and read enable ( ren ) input. data is read from the fifo on every rising edge of rclk when ren is asserted. during asynchronous operation only the rd input is used to read data from the fifo. data is read on a rising edge of rd, the ren input should be tied to its active state, low. when asynchronous operation is selected on the output port the fifo must be configured for standard idt mode, and the oe input used to provide three-state control of the outputs, qn. the frequencies of both the rclk and the wclk signals may vary from 0 to f max with complete independence. there are no restrictions on the frequency of the one clock input with respect to the other. there are two possible timing modes of operation with these devices: idt standard mode and first word fall through (fwft) mode. in idt standard mode, the first word written to an empty fifo will not appear on the data output lines unless a specific read operation is performed. a read operation, which consists of activating ren and enabling a rising rclk edge, will shift the word from internal memory to the data output lines. in fwft mode, the first word written to an empty fifo is clocked directly to the data output lines after three transitions of the rclk signal. a ren does not have to be asserted for accessing the first word. however, subsequent
4 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 figure 1. single device configuration signal flow diagram words written to the fifo do require a low on ren for access. the state of the fwft/si input during master reset determines the timing mode in use. for applications requiring more data storage capacity than a single fifo can provide, the fwft timing mode permits depth expansion by chaining fifos in series (i.e. the data outputs of one fifo are connected to the corresponding data inputs of the next). no external logic is required. these fifos have five flag pins, ef / or (empty flag or output ready), ff / ir (full flag or input ready), hf (half-full flag), pae (programmable almost-empty flag) and paf (programmable almost-full flag). the ef and ff functions are selected in idt standard mode. the ir and or functions are selected in fwft mode. hf , pae and paf are always available for use, irrespective of timing mode. pae and paf can be programmed independently to switch at any point in memory. programmable offsets determine the flag switching threshold and can be loaded by two methods: parallel or serial. eight default offset settings are also provided, so that pae can be set to switch at a predefined number of locations from the empty boundary and the paf threshold can also be set at similar predefined values from the full boundary. the default offset values are set during master reset by the state of the fsel0, fsel1, and ld pins. for serial programming, sen together with ld on each rising edge of wclk, are used to load the offset registers via the serial input (si). for parallel programming, wen together with ld on each rising edge of wclk, are used to load the offset registers via d n . ren together with ld on each rising edge of rclk can be used to read the offsets in parallel from q n regardless of whether serial or parallel offset loading has been selected. during master reset ( mrs ) the following events occur: the read and write pointers are set to the first location of the fifo. the fwft pin selects idt standard mode or fwft mode. the partial reset ( prs ) also sets the read and write pointers to the first location of the memory. however, the timing mode, programmable flag programming method, and default or programmed offset settings existing before partial reset remain unchanged. the flags are updated according to the timing mode and offsets in effect. prs is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable. it is also possible to select the timing mode of the pae (programmable almost- empty flag) and paf (programmable almost-full flag) outputs. the timing modes can be set to be either asynchronous or synchronous for the pae and paf flags. (x36, x18, x9) data out (q 0 - q n ) (x36, x18, x9) data in (d 0 - d n ) master reset ( mrs ) read clock (rclk/rd*) read enable ( ren ) output enable ( oe ) empty flag/output ready ( ef / or ) programmable almost-empty ( pae ) write clock (wclk/wr*) write enable ( wen ) load ( ld ) full flag/input ready ( ff / ir ) programmable almost-full ( paf ) idt 72v3640 72v3650 72v3660 72v3670 72v3680 72v3690 partial reset ( prs ) first word fall through/ serial input (fwft/si) retransmit ( rt ) 4667 drw03 half-full flag ( hf ) serial enable( sen ) input width (iw) output width (ow) big-endian/little-endian ( be ) interspersed/ non-interspersed parity (ip) bus- matching (bm) serial clock (sclk)
5 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 bm iw ow write port width read port width l l l x36 x36 h l l x36 x18 h l h x36 x9 h h l x18 x36 h h h x9 x36 table 1 bus-matching configuration modes if asynchronous pae / paf configuration is selected, the pae is asserted low on the low-to-high transition of rclk. pae is reset to high on the low- to-high transition of wclk. similarly, the paf is asserted low on the low- to-high transition of wclk and paf is reset to high on the low-to-high transition of rclk. if synchronous pae / paf configuration is selected , the pae is asserted and updated on the rising edge of rclk only and not wclk. similarly, paf is asserted and updated on the rising edge of wclk only and not rclk. the mode desired is configured during masterreset by the state of the programmable flag mode (pfm) pin. the retransmit function allows data to be reread from the fifo more than once. a low on the rt input during a rising rclk edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. a zero-latency retransmit timing mode can be selected using the retransmit timing mode pin (rm). during master reset, a low on rm will select zero latency retransmit. a high on rm during master reset will select normal latency. if zero latency retransmit operation is selected, the first data word to be retransmitted will be placed on the output register with respect to the same rclk edge that initiated the retransmit based on rt being low. refer to figure 11 and 12 for retransmit timing with normal latency. refer to figure 13 and 14 for zero latency retransmit timing . the device can be configured with different input and output bus widths as shown in table 1. a big-endian/little-endian data word format is provided. this function is useful when data is written into the fifo in long word format (x36/x18) and read note: 1. pin status during master reset. out of the fifo in small word (x18/x9) format. if big-endian mode is selected, then the most significant byte (word) of the long word written into the fifo will be read out of the fifo first, followed by the least significant byte. if little-endian format is selected, then the least significant byte of the long word written into the fifo will be read out first, followed by the most significant byte. the mode desired is configured during master reset by the state of the big-endian ( be ) pin. see figure 4 for bus-matching byte arrangement . the interspersed/non-interspersed parity (ip) bit function allows the user to select the parity bit in the word loaded into the parallel port (d 0 -dn) when programming the flag offsets. if interspersed parity mode is selected, then the fifo will assume that the parity bit is located in bit positions d8, d17, d26 and d35 during the parallel programming of the flag offsets. if non-interspersed parity mode is selected, then d8, d17 and d26 are assumed to be valid bits and d32, d33, d34 and d35 are ignored. ip mode is selected during master reset by the state of the ip input pin. interspersed parity control only has an effect during parallel programming of the offset registers. it does not effect the data written to and read from the fifo. a jtag test port is provided, here the fifo has fully functional boundary scan feature, compliant with ieee 1149.1 standard test access port and boundary scan architecture. if, at any time, the fifo is not actively performing an operation, the chip will automatically power down. once in the power down state, the standby supply current consumption is minimized. initiating any operation (by activating control inputs) will immediately take the device out of the power down state. the idt72v3640/72v3650/72v3660/72v3670/72v3680/72v3690 are fabricated using idt?s high speed submicron cmos technology.
6 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 pin description (tqfp and pbga packages) symbol name i/o description bm (1) bus-matching i bm works with iw and ow to select the bus sizes for both write and read ports. see table 1 for bus size configuration. be (1) big-endian/ i during master reset, a low on be will select big-endian operation. a high on be during master reset will little-endian select little-endian format. d 0 ?d 35 data inputs i data inputs for a 36-, 18- or 9-bit bus. when in 18- or 9-bit mode, the unused input pins are in a don?t care state. ef / or empty flag/ o in the idt standard mode, the ef function is selected. ef indicates whether or not the fifo memory is empty. output ready in fwft mode, the or function is selected. or indicates whether or not there is valid data available at the outputs. ff / ir full flag/ o in the idt standard mode, the ff function is selected. ff indicates whether or not the fifo memory is full. in the input ready fwft mode, the ir function is selected. ir indicates whether or not there is space available for writing to the fifo memory. fsel0 (1) flag select bit 0 i during master reset, this input along with fsel1 and the ld pin, will select the default offset values for the programmable flags pae and paf . there are up to eight possible settings available. fsel1 (1) flag select bit 1 i during master reset, this input along with fsel0 and the ld pin will select the default offset values for the programmable flags pae and paf . there are up to eight possible settings available. fwft/si first word fall i during master reset, selects first word fall through or idt standard mode. after master reset, this pin functions through/serial in as a serial input for loading offset registers. hf half-full flag o hf indicates whether the fifo memory is more or less than half-full. ip (1) interspersed parity i during master reset, a low on ip will select non-interspersed parity mode. a high will select interspersed parity mode. interspersed parity control only has an effect during parallel programming of the offset registers. it does not effect the data written to and read from the fifo. iw (1) input width i this pin, along with ow and mb, selects the bus width of the write port. see table 1 for bus size configuration. ld load i this is a dual purpose pin. during master reset, the state of the ld input along with fsel0 and fsel1, determines one of eight default offset values for the pae and paf flags, along with the method by which these offset registers can be programmed, parallel or serial (see table 2). after master reset, this pin enables writing to and reading from the offset registers. oe output enable i oe controls the output impedance of q n. ow (1) output width i this pin, along with iw and bm, selects the bus width of the read port. see table 1 for bus size configuration. mrs master reset i mrs initializes the read and write pointers to zero and sets the output register to all zeroes. during master reset, the fifo is configured for either fwft or idt standard mode, bus-matching configurations, one of eight progammable flag default settings, serial or parallel programming of the offset settings, big-endian/little-endian format, zero latency timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes. pae programmable o pae goes low if the number of words in the fifo memory is less than offset n, which is stored in the empty offset almost-empty flag register. pae goes high if the number of words in the fifo memory is greater than or equal to offset n. paf programmable o paf goes high if the number of free locations in the fifo memory is more than offset m, which is stored in the almost-full flag full offset register. paf goes low if the number of free locations in the fifo memory is less than or equal to m. pfm (1) programmable i during master reset, a low on pfm will select asynchronous programmable flag timing mode. a high on pfm flag mode will select synchronous programmable flag timing mode. prs partial reset i prs initializes the read and write pointers to zero and sets the output register to all zeroes. during partial reset, the existing mode (idt or fwft), programming method (serial or parallel), and programmable flag settings are all retained. q 0 ?q 35 data outputs o data outputs for an 36-, 18- or 9-bit bus. when in 18- or 9-bit mode, the unused output pins are in a don?t care state. outputs are not 5v tolerant regardless of the state of oe . rclk/ read clock/ i if synchronous operation of the read port has been selected, when enabled by ren , the rising edge of rclk rd read strobe reads data from the fifo memory and offsets from the programmable registers. if ld is low, the values loaded into the offset registers is output on a rising edge of rclk.if asynchronous operation of the read port has been selected, a rising edge on rd reads data from the fifo in an asynchronous manner. ren should be tied low. asynchronous operation of the rclk/rd input is only available in the pbga package. ren read enable i ren enables rclk for reading data from the fifo memory and offset registers. rm (1) retransmit timing i during master reset, a low on rm will select zero latency retransmit timing mode. a high on rm will select mode normal latency mode. rt retransmit i rt asserted on the rising edge of rclk initializes the read pointer to zero, sets the ef flag to low ( or to high in fwft mode) and does not disturb the write pointer, programming method, existing timing mode or programmable flag settings. rt is useful to reread data from the first physical location of the fifo. note: 1. inputs should not change state after master reset.
7 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 note: 1. inputs should not change state after master reset. 2. these pins are for the jtag port. please refer to pages 42-45 and figures 31-33. pin description (pbga package only) symbol name i/o description asyr (1) asynchronous i a high on this input during master reset will select synchronous read operation for the output port. a low read port will select asynchronous operation. if asynchronous is selected the fifo must operate in idt standard mode. asyw (1) asynchronous i a high on this input during master reset will select synchronous write operation for the input port. a low write port will select asynchronous operation. tck (2) jtag clock i clock input for jtag function. one of four terminals required by ieee standard 1149.1-1990. test operations of the device are synchronous to tck. data from tms and tdi are sampled on the rising edge of tck and outputs change on the falling edge of tck. if the jtag function is not used this signal needs to be tied to gnd. tdi (2) jtag test data i one of four terminals required by ieee standard 1149.1-1990. during the jtag boundary scan operation, test data input serially loaded via the tdi on the rising edge of tck to either the instruction register, id register and bypass register. an internal pull-up resistor forces tdi high if left unconnected. tdo (2) jtag test data o one of four terminals required by ieee standard 1149.1-1990. during the jtag boundary scan operation, test data output serially loaded output via the tdo on the falling edge of tck from either the instruction register, id register and bypass register. this output is high impedance except when shifting, while in shift-dr and shift-ir controller states. tms (2) jtag mode select i tms is a serial input pin. one of four terminals required by ieee standard 1149.1-1990. tms directs the device through its tap controller states. an internal pull-up resistor forces tms high if left unconnected. trst (2) jtag reset i trst is an asynchronous reset pin for the jtag controller. the jtag tap controller does not automatically reset upon power-up, thus it must be reset by either this signal or by setting tms= high for five tck cycles. if the tap controller is not properly reset then the fifo outputs will always be in high-impedance. if the jtag function is used but the user does not want to use trst , then trst can be tied with mrs to ensure proper fifo operation. if the jtag function is not used then this signal needs to be tied to gnd. pin description-continued (tqfp & pbga packages) sen serial enable i sen enables serial loading of programmable flag offsets. wclk/ write clock/ i if synchronous operation of the write port has been selected, when enabled by wen , the rising edge of wclk wr write strobe writes data into the fifo. if asynchronous operation of the write port has been selected, wr writes data into t he fifo on a rising edge in an asynchronous manner, ( wen should be tied to its active state). asynchronous operation of the wclk/wr input is only available in the pbga package. wen write enable i wen enables wclk for writing data into the fifo memory and offset registers. v cc +3.3v supply i these are v cc supply inputs and must be connected to the 3.3v supply rail. symbol name i/o description note: 1. inputs should not change state after master reset.
8 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 absolute maximum ratings symbol rating com?l & ind?l unit v term (2) terminal voltage ?0.5 to +4.5 v with respect to gnd t stg storage ?55 to +125 c temperature i out dc output current ?50 to +50 ma notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminal only. notes: 1. with output deselected, ( oe v ih ). 2. characterized values, not currently tested. dc electrical characteristics (commercial: v cc = 3.3v 0.15v, t a = 0 c to +70 c;industrial: v cc = 3.3v 0.15v, t a = -40 c to +85 c; jedec jesd8-a compliant) capacitance (t a = +25 c, f = 1.0mhz) symbol parameter (1) conditions max. unit c in (2) input v in = 0v 10 pf capacitance c out (1,2) output v out = 0v 10 pf capacitance symbol parameter min. typ. max. unit v cc (1) supply voltage com?l/ind?l 3.15 3.3 3.45 v gnd supply voltage com?l/ind?l 0 0 0 v v ih (2) input high voltage com?l/ind?l 2.0 ? 5.5 v v il (3) input low voltage com?l/ind?l ? ? 0.8 v t a operating temperature 0 ? 70 c commercial t a operating temperature -40 ? 85 c industrial notes: 1. v cc = 3.3v 0.15v, jedec jesd8-a compliant. 2. outputs are not 5v tolerant. 3. 1.5v undershoots are allowed for 10ns once per cycle. idt72v3640l idt72v3650l idt72v3660l idt72v3670l idt72v3680l idt72v3690l commercial and industrial (1) t clk = 6, 7.5, 10, 15 ns symbol parameter min. max. unit i li (2) input leakage current ?1 1 a i lo (3) output leakage current ?10 10 a v oh output logic ?1? voltage, i oh = ?2 ma 2.4 ? v v ol output logic ?0? voltage, i ol = 8 ma ? 0.4 v i cc1 (4,5,6) active power supply current ? 40 ma i cc2 (4,7) standby current ? 15 ma notes : 1. industrial temperature range product for the 15ns speed grade is available as a standard device. all other speed grades are a vailable by special order. 2. measurements with 0.4 v in v cc . 3. oe v ih, 0.4 v out v cc. 4. tested with outputs open (i out = 0). 5. rclk and wclk toggle at 20 mhz and data inputs switch at 10 mhz. 6. typical i cc1 = 4.2 + 1.4*f s + 0.002*c l *f s (in ma) with v cc = 3.3v, t a = 25 c, f s = wclk frequency = rclk frequency (in mhz, using ttl levels), data switching at f s /2, c l = capacitive load (in pf). 7. all inputs = v cc - 0.2v or gnd + 0.2v, except rclk and wclk, which toggle at 20 mhz. recommended dc operating conditions
9 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 ac electrical characteristics (1) synchronous timing (commercial: v cc = 3.3v 0.15v, t a = 0 c to +70 c;industrial: v cc = 3.3v 0.15v, t a = -40 c to +85 c; jedec jesd8-a compliant) notes: 1. all ac timings apply to both standard idt mode and first word fall through mode. 2. industrial temperature range is available by special order for speed grades faster than 15ns. 3. pulse widths less than minimum values are not allowed. 4. values guaranteed by design, not currently tested. 5. tqfp package only: for speed grades 7.5ns, 10ns and 15ns, the minimum for t a , t oe , and t ohz is 2ns. commercial commercial commercial com?l & ind?l (2) pbga & tqfp pbga & tqfp tqfp only tqfp only idt72v3640l6 idt72v3640l7-5 idt72v3640l10 idt72v3640l15 idt72v3650l6 idt72v3650l7-5 idt72v3650l10 idt72v3650l15 idt72v3660l6 idt72v3660l7-5 idt72v3660l10 idt72v3660l15 idt72v3670l6 idt72v3670l7-5 idt72v3670l10 idt72v3670l15 idt72v3680l6 idt72v3680l7-5 idt72v3680l10 idt72v3680l15 idt72v3690l6 idt72v3690l7-5 idt72v3690l10 idt72v3690l15 symbol parameter min. max. min. max. min. max. min. max. unit f s clock cycle frequency ? 166 ? 133.3 ? 100 ? 66.7 m h z t a data access time (5) 141 (5) 51 (5) 6.5 1 (5) 10 ns t clk clock cycle time 6 ? 7.5 ? 10 ? 15 ? ns t clkh clock high time 2.7 ? 3.5 ? 4.5 ? 6 ? ns t clkl clock low time 2.7 ? 3.5 ? 4.5 ? 6 ? ns t ds data setup time 2 ? 2.5 ? 3.5 ? 4 ? ns t dh data hold time 0.5 ? 0.5 ? 0.5 ? 1 ? ns t ens enable setup time 2 ? 2.5 ? 3.5 ? 4 ? ns t enh enable hold time 0.5 ? 0.5 ? 0.5 ? 1 ? ns t lds load setup time 3 ? 3.5 ? 3.5 ? 4 ? ns t ldh load hold time 0.5 ? 0.5 ? 0.5 ? 1 ? ns t rs reset pulse width (3) 10 ? 10 ? 10 ? 15 ? ns t rss reset setup time 15 ? 15 ? 15 ? 15 ? ns t rsr reset recovery time 10 ? 10 ? 10 ? 15 ? ns t rsf reset to flag and output time ? 15 ? 15 ? 15 ? 15 ns t rts retransmit setup time 3 ? 3.5 ? 3.5 ? 4 ? ns t olz output enable to output in low z (4) 0?0?0 ?0?ns t oe output enable to output valid (5) 141 (5) 61 (5) 61 (5) 8ns t ohz output enable to output in high-z (4, 5) 141 (5) 61 (5) 61 (5) 8ns t wff write clock to ff or ir ?4?5?6.5?10ns t ref read clock to ef or or ?4?5?6.5?10ns t pafa clock to asynchronous programmable almost-full flag ? 10 ? 12.5 ? 16 ? 20 ns t pafs write clock to synchronous programmable almost-full flag ? 4 ? 5 ? 6.5 ? 10 ns t paea clock to asynchronous programmable almost-empty flag ? 10 ? 12.5 ? 16 ? 20 ns t paes read clock to synchronous programmable almost-empty flag ? 4 ? 5 ? 6.5 ? 10 ns t hf clock to hf ? 10 ? 12.5 ? 16 ? 20 ns t skew1 skew time between rclk and wclk for ef / or and ff / ir 4?5?7 ?9?ns t skew2 skew time between rclk and wclk for pae and paf 5?7?10 ?14?ns
10 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 ac electrical characteristics (1) asynchronous timing (commercial: v cc = 3.3v 0.15v, t a = 0 c to +70 c;industrial: v cc = 3.3v 0.15v, t a = -40 c to +85 c; jedec jesd8-a compliant) commercial idt72v3640l6 idt72v3640l7-5 idt72v3650l6 idt72v3650l7-5 idt72v3660l6 idt72v3660l7-5 idt72v3670l6 idt72v3670l7-5 idt72v3680l6 idt72v3680l7-5 idt72v3690l6 idt72v3690l7-5 symbol parameter min. max. min. max. unit f a (4) cycle frequency (asynchronous mode) ? 100 ? 83 mhz t aa (4) data access time 0.6 8 0.6 10 ns t cyc (4) cycle time 10 ? 12 ? ns t cyh (4) cycle high time 4.5 ? 5 ? ns t cyl (4) cycle low time 4.5 ? 5 ? ns t rpe (4) read pulse after ef high 8 ? 10 ? ns t ffa (4) clock to asynchronous ff ?8? 10ns t efa (4) clock to asynchronous ef ?8? 10ns t pafa (4) clock to asynchronous programmable almost-full flag ? 8 ? 10 ns t paea (4) clock to asynchronous programmable almost-empty flag ? 8 ? 10 ns notes: 1. all ac timings apply to both standard idt mode and first word fall through mode. 2. pulse widths less than minimum values are not allowed. 3. values guaranteed by design, not currently tested. 4. paramaeters apply to the pbga package only.
11 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 4667 drw04 330 ? 30pf* 510 ? 3.3v d.u.t. input pulse levels gnd to 3.0v input rise/fall times 3ns (1) input timing reference levels 1.5v output reference levels 1.5v output load for t clk = 10ns, 15 ns see figure 2a output load for t clk = 6ns, 7.5ns see figure 2b & 2c ac test conditions figure 2b. ac test load figure 2c. lumped capacitive load, typical derating ac test loads - 6ns, 7.5ns speed grades figure 2a. output load * includes jig and scope capacitances. ac test loads - 10ns, 15ns speed grades note: 1. for 166mhz and 133mhz operation input rise/fall times are 1.5ns. 4667 drw04a 50 ? 1.5v i/o z 0 = 50 ? 4667 drw04b 6 5 4 3 2 1 20 30 50 80 100 200 ca p acitance (p f ) t cd (typical, ns) v ih oe v il t oe & t olz v cc 2 v cc 2 100mv 100mv t ohz 100mv 100mv output normally low output normally high v ol v oh v cc 2 v cc 2 4667 drw04c output enable output disable output enable & disable timing note: 1. ren is high.
12 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 if the fifo is full, the first read operation will cause ff to go high. subsequent read operations will cause paf and hf to go high at the conditions described in table 3. if further read operations occur, without write operations, pae will go low when there are n words in the fifo, where n is the empty offset value. continuing read operations will cause the fifo to become empty. when the last word has been read from the fifo, the ef will go low inhibiting further read operations. ren is ignored when the fifo is empty. when configured in idt standard mode, the ef and ff outputs are double register-buffered outputs. relevant timing diagrams for idt standard mode can be found in figure 7,8,11 and 13. first word fall through mode (fwft) in this mode, the status flags, ir , paf , hf , pae , and or operate in the manner outlined in table 4. to write data into to the fifo, wen must be low. data presented to the data in lines will be clocked into the fifo on subsequent transitions of wclk. after the first write is performed, the output ready ( or ) flag will go low. subsequent writes will continue to fill up the fifo. pae will go high after n + 2 words have been loaded into the fifo, where n is the empty offset value. the default setting for these values are stated in the footnote of table 2. this parameter is also user programmable. see section on programmable flag offset loading. if one continued to write data into the fifo, and we assumed no read operations were taking place, the hf would toggle to low once the 514th word for the idt72v3640, 1,026th word for the idt72v3650, 2,050th word for the idt72v3660, 4,098th word for the idt72v3670, 8,194th word for the idt72v3680, 16,386th word for the idt72v3690, respectively was written into the fifo. continuing to write data into the fifo will cause the paf to go low. again, if no reads are performed, the paf will golow after (1,025-m) writes for the idt72v3640, (2,049-m) writes for the idt72v3650, (4,097-m) writes for the idt72v3660 and (8,193-m) writes for the idt72v3670, (16,385-m) writes for the idt72v3680 and (32,769-m) writes for the idt72v3690, where m is the full offset value. the default setting for these values are stated in the footnote of table 2. when the fifo is full, the input ready ( ir ) flag will go high, inhibiting further write operations. if no reads are performed after a reset, ir will go high after d writes to the fifo. d = 1,025 writes for the idt72v3640, 2,049 writes for the idt72v3650, 4,097 writes for the idt72v3660 and 8,193 writes for the idt72v3670,16,385 writes for the idt72v3680 and 32,769 writes for the idt72v3690, respectively. note that the additional word in fwft mode is due to the capacity of the memory plus output register. if the fifo is full, the first read operation will cause the ir flag to go low. subsequent read operations will cause the paf and hf to go high at the conditions described in table 4. if further read operations occur, without write operations, the pae will go low when there are n + 1 words in the fifo, where n is the empty offset value. continuing read operations will cause the fifo to become empty. when the last word has been read from the fifo, or will go high inhibiting further read operations. ren is ignored when the fifo is empty. when configured in fwft mode, the or flag output is triple register- buffered, and the ir flag output is double register-buffered. relevant timing diagrams for fwft mode can be found in figure 9, 10, 12, and 14. functional description timing modes: idt standard vs first word fall through (fwft) mode the idt72v3640/72v3650/72v3660/72v3670/72v3680/72v3690 sup- port two different timing modes of operation: idt standard mode or first word fall through (fwft) mode. the selection of which mode will operate is determined during master reset, by the state of the fwft/si input. if, at the time of master reset, fwft/si is low, then idt standard mode will be selected. this mode uses the empty flag ( ef ) to indicate whether or not there are any words present in the fifo. it also uses the full flag function ( ff ) to indicate whether or not the fifo has any free space for writing. in idt standard mode, every word read from the fifo, including the first, must be requested using the read enable ( ren ) and rclk. if, at the time of master reset, fwft/si is high, then fwft mode will be selected. this mode uses output ready ( or ) to indicate whether or not there is valid data at the data outputs (q n) . it also uses input ready ( ir ) to indicate whether or not the fifo has any free space for writing. in the fwft mode, the first word written to an empty fifo goes directly to q n after three rclk rising edges, ren = low is not necessary. subsequent words must be accessed using the read enable ( ren ) and rclk. various signals, both input and output signals operate differently depending on which timing mode is in effect. idt standard mode in this mode, the status flags, ff , paf , hf , pae , and ef operate in the manner outlined in table 3. to write data into to the fifo, write enable ( wen ) must be low. data presented to the data in lines will be clocked into the fifo on subsequent transitions of the write clock (wclk). after the first write is performed, the empty flag ( ef ) will go high. subsequent writes will continue to fill up the fifo. the programmable almost-empty flag ( pae ) will go high after n + 1 words have been loaded into the fifo, where n is the empty offset value. the default setting for these values are stated in the footnote of table 2. this parameter is also user programmable. see section on programmable flag offset loading. if one continued to write data into the fifo, and we assumed no read operations were taking place, the half-full flag ( hf ) would toggle to low once the 513rd word for idt72v3640, 1,025th word for idt72v3650, 2,049th word for idt72v3660, 4,097th word for idt72v3670, 8,193th word for the idt72v3680 and 16,385th word for the idt72v3690, respectively was written into the fifo. continuing to write data into the fifo will cause the programmable almost-full flag ( paf ) to go low. again, if no reads are performed, the paf will go low after (1,024-m) writes for the idt72v3640, (2,048-m) writes for the idt72v3650, (4,096-m) writes for the idt72v3660, (8,192-m) writes for the idt72v3670, (16,384-m) writes for the idt72v3680 and (32,768-m) writes for the idt72v3690. the offset ?m? is the full offset value. the default setting for these values are stated in the footnote of table 2. this parameter is also user programmable. see section on programmable flag offset loading. when the fifo is full, the full flag ( ff ) will go low, inhibiting further write operations. if no reads are performed after a reset, ff will go low after d writes to the fifo. d = 1,024 writes for the idt72v3640, 2,048 writes for the idt72v3650, 4,096 writes for the idt72v3660, 8,192 writes for the idt72v3670, 16,384 writes for the idt72v3680 and 32,768 writes for the idt72v3690, respectively.
13 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 programming flag offsets full and empty flag offset values are user programmable. the idt72v3640/ 72v3650/72v3660/72v3670/72v3680/72v3690 have internal registers for these offsets. there are eight default offset values selectable during master reset. these offset values are shown in table 2. offset values can also be programmed into the fifo in one of two ways; serial or parallel loading method. the selection of the loading method is done using the ld (load) pin. during master reset, the state of the ld input determines whether serial or parallel flag offset programming is enabled. a high on ld during master reset selects serial loading of offset values. a low on ld during master reset selects parallel loading of offset values. in addition to loading offset values into the fifo, it is also possible to read the current offset values. offset values can be read via the parallel output port q 0 -qn, regardless of the programming mode selected (serial or parallel). it is not possible to read the offset values in serial fashion. figure 3, programmable flag offset programming sequence, summaries the control pins and sequence for both serial and parallel programming modes. for a more detailed description, see discussion that follows. the offset registers may be programmed (and reprogrammed) any time after master reset, regardless of whether serial or parallel programming has been selected. valid programming ranges are from 0 to d-1. synchronous vs asynchronous programmable flag timing selection the idt72v3640/72v3650/72v3660/72v3670/72v3680/72v3690 can be configured during the master reset cycle with either synchronous or asynchronous timing for paf and pae flags by use of the pfm pin. if synchronous paf / pae configuration is selected (pfm, high during mrs ), the paf is asserted and updated on the rising edge of wclk only and not rclk. similarly, pae is asserted and updated on the rising edge of rclk only and not wclk. for detail timing diagrams, see figure 17 for synchronous paf timing and figure 18 for synchronous pae timing. if asynchronous paf / pae configuration is selected (pfm, low during mrs ), the paf is asserted low on the low-to-high transition of wclk and paf is reset to high on the low-to-high transition of rclk. similarly, pae is asserted low on the low-to-high transition of rclk. pae is reset to high on the low-to-high transition of wclk. for detail timing diagrams, see figure 19 for asynchronous paf timing and figure 20 for asynchronous pae timing. idt72v3640, 72v3650 ld fsel1 fsel0 offsets n,m lh l511 l l h 255 l l l 127 lh h63 hl l31 hh l15 hl h7 hh h3 ld fsel1 fsel0 program mode h x x serial (3) l x x parallel (4) idt72v3660, 72v3670, 72v3680, 72v3690 ld fsel1 fsel0 offsets n,m h l l 1,023 lh l511 l l h 255 l l l 127 lh h63 hh l31 hl h15 hh h7 ld fsel1 fsel0 program mode h x x serial (3) l x x parallel (4) table 2 default programmable flag offsets notes: 1. n = empty offset for pae . 2. m = full offset for paf . 3. as well as selecting serial programming mode, one of the default values will also be loaded depending on the state of fsel0 & fsel1. 4. as well as selecting parallel programming mode, one of the default values will also be loaded depending on the state of fsel0 & fsel1.
14 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 0 (n+2) to 4,097 4,098 to (8,193(m+1)) 8,193 idt72v3670 4667 drw05 00 (n+2) to 8,193 (n+2) to 16,385 8,194 to (16,385-(m+1)) 16,386 to (32,769-(m+1)) 16,385 32,769 idt72v3680 idt72v3690 i r p a f h f p a e o r lh hlh lh hl l lh h hl lhl hl l l lhl hl lhl number of words in fifo table 4 ? status flags for fwft mode table 3 ? status flags for idt standard mode f f p a f h f p a e e f hh hl l hh hl h hh h hh hhlh h h l lhh l l lhh 0 1 to n (1) (n+1) to 512 513 to (1,024-(m+1)) (1,024-m) to 1,023 1,024 idt72v3640 00 (n+1) to 1,024 (n+1) to 2,048 1,025 to (2,048-(m+1)) 2,049 to (4,096-(m+1)) (2,048-m) to 2,047 (4,096m) to 4,095 2,048 4,096 idt72v3650 idt72v3660 f f p a f h f p a e e f hh hl l hh hl h hh h hh hhlh h h l lhh l l lhh 0 (n+1) to 4,096 4,097 to (8,192-(m+1)) (8,192-m) to 8,191 8,192 idt72v3670 00 (n+1) to 8,192 (n+1) to 16,384 8,193 to (16,384-(m+1)) 16,385 to (32,768-(m+1)) (16,384-m) to 16,383 (32,768-m) to 32,767 16,384 32,768 idt72v3680 idt72v3690 number of words in fifo 1 to n (1) 1 to n (1) 1 to n (1) 1 to n (1) 1 to n (1) number of words in fifo 0 1 to n+1 (n+2) to 513 514 to (1,025-(m+1)) (1,025-m) to 1,024 1,025 idt72v3640 00 (n+2) to 1,025 (n+2) to 2,049 1,026 to (2,049-(m+1)) 2,050 to (4,097-(m+1)) (2,049-m) to 2,048 (4,097m) to 4,096 2,049 4,097 idt72v3650 idt72v3660 number of words in fifo i r p a f h f p a e o r lh hlh lh hl l lh h hl lhl hl l l lhl hl lhl 1 to n+1 1 to n+1 1 to n+1 1 to n+1 1 to n+1 (8,194-m) to 8,192 (16,385-m) to 16,384 (32,769-m) to 32,768 note: 1. see table 2 for values for n, m. note: 1. see table 2 for values for n, m.
15 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 figure 3. programmable flag offset programming sequence notes: 1. the programming method can only be selected at master reset. 2. parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 3. the programming sequence applies to both idt standard and fwft modes. wclk rclk x x xx x x xx l d 0 0 x 1 1 1 0 w e n 0 1 1 0 x 1 1 r e n 1 0 1 x 0 1 1x s e n 1 1 1 x x x 0 no operation write memory read memory no operation parallel write to registers: empty offset (lsb) empty offset (msb) full offset (lsb) full offset (msb) idt72v3640 idt72v3650 idt72v3660 idt72v3670 idt72v3680 idt72v3690 parallel read from registers: empty offset (lsb) empty offset (msb) full offset (lsb) full offset (msb) serial shift into registers: 20 bits for the 72v3640 22 bits for the 72v3650 24 bits for the 72v3660 26 bits for the 72v3670 28 bits for the 72v3680 30 bits for the 72v3690 1 bit for each rising wclk edge starting with empty offset (lsb) ending with full offset (msb) 4667 drw06
16 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 # of bits used: 10 bits for the idt72v3640 11 bits for the idt72v3650 12 bits for the idt72v3660 13 bits for the idt72v3670 14 bits for the idt72v3680 15 bits for the idt72v3690 note: all unused bits of the lsb & msb are don't care d/q17 d/q0 d/q8 empty offset register ( pae ) # of bits used 2 3 4 5 6 7 9 10 11 12 13 14 15 16 1st parallel offset write/read cycle 2 3 4 5 6 7 8 12 13 14 15 16 17 11 interspersed parity 17 10 1 1 8 d/q35 d/q19 9 d/q17 d/q0 d/q8 full offset register ( paf ) # of bits used 2 3 4 5 6 7 9 10 11 12 13 14 15 16 2nd parallel offset write/read cycle 2 3 4 5 6 7 8 12 13 14 15 16 17 11 interspersed parity 17 10 1 1 8 9 idt72v3640/50/60/70/80/90 ? x36 bus width d/q35 d/q19 d/q17 d/q0 d/q16 empty offset (lsb) register ( pae ) data inputs/outputs # of bits used 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1st parallel offset write/read cycle data inputs/outputs 2nd parallel offset write/read cycle 1 2 3 4 5 6 7 8 10 11 12 13 14 15 9 full offset (lsb) register ( paf ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 10 11 12 13 14 15 9 non-interspersed parity interspersed parity d/q0 d/q8 d/q8 16 16 d/q17 d/q16 idt72v3640/50/60/70/80/90 ? x18 bus width 4667 drw07 non-interspersed parity non-interspersed parity d/q8 d/q0 empty offset register ( pae ) 1 2 3 4 5 6 7 8 1st parallel offset write/read cycle 2nd parallel offset write/read cycle d/q8 d/q0 empty offset register ( pae ) 9 10 11 12 13 14 15 16 3rd parallel offset write/read cycle d/q8 d/q0 full offset register ( paf ) 1 2 3 4 5 6 7 8 4th parallel offset write/read cycle d/q8 d/q0 full offset register ( paf ) 9 10 11 12 13 14 15 idt72v3640/50/60/70/80/90 ? x9 bus width figure 3. programmable flag offset programming sequence (continued)
17 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 serial programming mode if serial programming mode has been selected, as described above, then programming of pae and paf values can be achieved by using a combination of the ld , sen , wclk and si input pins. programming pae and paf proceeds as follows: when ld and sen are set low, data on the si input are written, one bit for each wclk rising edge, starting with the empty offset lsb and ending with the full offset msb. a total of 20 bits for the idt72v3640, 22 bits for the idt72v3650, 24 bits for the idt72v3660, 26 bits for the idt72v3670, 28 bits for the idt72v3680 and 30 bits for the idt72v3690. see figure 15, serial loading of programmable flag registers , for the timing diagram for this mode. using the serial method, individual registers cannot be programmed selectively. pae and paf can show a valid status only after the complete set of bits (for all offset registers) has been entered. the registers can be reprogrammed as long as the complete set of new offset bits is entered. when ld is low and sen is high, no serial write to the registers can occur. write operations to the fifo are allowed before and during the serial programming sequence. in this case, the programming of all offset bits does not have to occur at once. a select number of bits can be written to the si input and then, by bringing ld and sen high, data can be written to fifo memory via d n by toggling wen . when wen is brought high with ld and sen restored to a low, the next offset bit in sequence is written to the registers via si. if an interruption of serial programming is desired, it is sufficient either to set ld low and deactivate sen or to set sen low and deactivate ld . once ld and sen are both restored to a low level, serial offset programming continues. from the time serial programming has begun, neither programmable flag will be valid until the full set of bits required to fill all the offset registers has been written. measuring from the rising wclk edge that achieves the above criteria; paf will be valid after two more rising wclk edges plus t paf , pae will be valid after the next two rising rclk edges plus t pae plus t skew2 . it is only possible to read the flag offset values via the parallel output port qn. parallel mode if parallel programming mode has been selected, as described above, then programming of pae and paf values can be achieved by using a combination of the ld , wclk , wen and d n input pins. programming pae and paf proceeds as follows: ld and wen must be set low. for x36 bit input bus width, data on the inputs d n are written into the empty offset register on the first low- to-high transition of wclk. upon the second low-to-high transition of wclk, data are written into the full offset register. the third transition of wclk writes, once again, to the empty offset register. for x18 bit input bus width, data on the inputs dn are written into the empty offset register lsb on the first low-to-high transition of wclk. upon the 2nd low-to-high transition of wclk data are written into the empty offset register msb. the third transition of wclk writes to the full offset register lsb, the fourth transition of wclk then writes to the full offset register msb. the fifth transition of wclk writes once again to the empty offset register lsb. a total of four writes to the offset registers is required to load values using a x18 input bus width. for an input bus width of x9 bits, a total of six write cycles to the offset registers is required to load values. see figure 3, programmable flag offset programming sequence . see figure 16, parallel loading of programmable flag registers , for the timing diagram for this mode. the act of writing offsets in parallel employs a dedicated write offset register pointer. the act of reading offsets employs a dedicated read offset register pointer. the two pointers operate independently; however, a read and a write should not be performed simultaneously to the offset registers. a master reset initializes both pointers to the empty offset (lsb) register. a partial reset has no effect on the position of these pointers. write operations to the fifo are allowed before and during the parallel programming sequence. in this case, the programming of all offset registers does not have to occur at one time. one, two or more offset registers can be written and then by bringing ld high, write operations can be redirected to the fifo memory. when ld is set low again, and wen is low, the next offset register in sequence is written to. as an alternative to holding wen low and toggling ld , parallel programming can also be interrupted by setting ld low and toggling wen . note that the status of a programmable flag ( pae or paf ) output is invalid during the programming process. from the time parallel programming has begun, a programmable flag output will not be valid until the appropriate offset word has been written to the register(s) pertaining to that flag. measuring from the rising wclk edge that achieves the above criteria; paf will be valid after two more rising wclk edges plus t paf , pae will be valid after the next two rising rclk edges plus t pae plus t skew2 . the act of reading the offset registers employs a dedicated read offset register pointer. the contents of the offset registers can be read on the q 0 -q n pins when ld is set low and ren is set low. for x36 output bus width, data are read via q n from the empty offset register on the first low-to-high transition of rclk. upon the second low-to-high transition of rclk, data are read from the full offset register. the third transition of rclk reads, once again, from the empty offset register. for x18 output bus width, a total of four read cycles are required to obtain the values of the offset registers. starting with the empty offset register lsb and finishing with the full offset register msb. for x9 output bus width, a total of six read cycles must be performed on the offset registers. see figure 3, programmable flag offset programming sequence . see figure 17, parallel read of programmable flag registers , for the timing diagram for this mode. it is permissible to interrupt the offset register read sequence with reads or writes to the fifo. the interruption is accomplished by deasserting ren , ld , or both together. when ren and ld are restored to a low level, reading of the offset registers continues where it left off. it should be noted, and care should be taken from the fact that when a parallel read of the flag offsets is performed, the data word that was present on the output lines qn will be overwritten. parallel reading of the offset registers is always permitted regardless of which timing mode (idt standard or fwft modes) has been selected. retransmit operation the retransmit operation allows data that has already been read to be accessed again. there are 2 modes of retransmit operation, normal latency and zero latency. there are two stages to retransmit: first, a setup procedure that resets the read pointer to the first location of memory, then the actual retransmit, which consists of reading out the memory contents, starting at the beginning of memory. retransmit setup is initiated by holding rt low during a rising rclk edge. ren and wen must be high before bringing rt low. when zero latency is utilized, ren does not need to be high before bringing rt low. at least two words, but no more than d - 2 words should have been written into the fifo, and read from the fifo, between reset (master or partial) and the time of retransmit setup. d = 1,024 for the idt72v3640, 2,048 for the idt72v3650, 4,096 for the idt72v3660, 8,192 for the idt72v3670, 16,384 for the idt72v3680 and 32,768 for the idt72v3690. in fwft mode, d = 1,025 for the idt72v2640, 2,049 for the idt72v3650, 4,097 for the idt72v3660, 8,193 for the idt72v3670, 16,385 for the idt72v3680 and 32,769 for the idt72v3690. if idt standard mode is selected, the fifo will mark the beginning of the retransmit setup by setting ef low. the change in level will only be noticeable
18 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 if ef was high before setup. during this period, the internal read pointer is initialized to the first location of the ram array. when ef goes high, retransmit setup is complete and read operations may begin starting with the first location in memory. since idt standard mode is selected, every word read including the first word following retransmit setup requires a low on ren to enable the rising edge of rclk. see figure 11, retransmit timing (idt standard mode) , for the relevant timing diagram. if fwft mode is selected, the fifo will mark the beginning of the retransmit setup by setting or high. during this period, the internal read pointer is set to the first location of the ram array. when or goes low, retransmit setup is complete; at the same time, the contents of the first location appear on the outputs. since fwft mode is selected, the first word appears on the outputs, no low on ren is necessary. reading all subsequent words requires a low on ren to enable the rising edge of rclk. see figure 12, retransmit timing (fwft mode) , for the relevant timing diagram. for either idt standard mode or fwft mode, updating of the pae , hf and paf flags begin with the rising edge of rclk that rt is setup. pae is synchronized to rclk, thus on the second rising edge of rclk after rt is setup, the pae flag will be updated. hf is asynchronous, thus the rising edge of rclk that rt is setup will update hf . paf is synchronized to wclk, thus the second rising edge of wclk that occurs t skew after the rising edge of rclk that rt is setup will update paf . rt is synchronized to rclk. the retransmit function has the option of two modes of operation, either ?normal latency? or ?zero latency?. figure 11 and figure 12 mentioned previously, relate to ?normal latency?. figure 13 and figure 14 show ?zero latency? retransmit operation. zero latency basically means that the first data word to be retransmitted, is placed onto the output register with respect to the rclk pulse that initiated the retransmit.
19 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 signal description inputs: data in (d 0 - d n ) data inputs for 36-bit wide data (d 0 - d 35 ), data inputs for 18-bit wide data (d 0 - d 17 ) or data inputs for 9-bit wide data (d 0 - d 8 ). controls: master reset ( mrs ) a master reset is accomplished whenever the mrs input is taken to a low state. this operation sets the internal read and write pointers to the first location of the ram array. pae will go low, paf will go high, and hf will go high. if fwft/si is low during master reset then the idt standard mode, along with ef and ff are selected. ef will go low and ff will go high. if fwft/si is high, then the first word fall through mode (fwft), along with ir and or , are selected. or will go high and ir will go low. all control settings such as ow, iw, bm, be , rm, pfm and ip are defined during the master reset cycle. during a master reset, the output register is initialized to all zeroes. a master reset is required after power up, before a write operation can take place. mrs is asynchronous. see figure 5, master reset timing , for the relevant timing diagram. partial reset ( prs ) a partial reset is accomplished whenever the prs input is taken to a low state. as in the case of the master reset, the internal read and write pointers are set to the first location of the ram array, pae goes low, paf goes high, and hf goes high. whichever mode is active at the time of partial reset, idt standard mode or first word fall through, that mode will remain selected. if the idt standard mode is active, then ff will go high and ef will go low. if the first word fall through mode is active, then or will go high, and ir will go low. following partial reset, all values held in the offset registers remain unchanged. the programming method (parallel or serial) currently active at the time of partial reset is also retained. the output register is initialized to all zeroes. prs is asynchronous. a partial reset is useful for resetting the device during the course of operation, when reprogramming programmable flag offset settings may not be convenient. see figure 6, partial reset timing , for the relevant timing diagram. asynchronous write ( asyw ) the write port can be configured for either synchronous or asynchronous mode of operation. if during master reset the asyw input is low, then asynchronous operation of the write port will be selected. during asynchronous operation of the write port the wclk input becomes wr input, this is the asynchronous write strobe input. a rising edge on wr will write data present on the dn inputs into the fifo. ( wen must be tied low when using the write port in asynchronous mode). when the write port is configured for asynchronous operation the full flag ( ff ) operates in an asynchronous manner, that is, the full flag will be updated based in both a write operation and read operation. note, if asynchronous mode is selected, fwft is not permissable. refer to figures 23, 24, 27 and 28 for relevant timing and operational waveforms. asynchronous read ( asyr ) the read port can be configured for either synchronous or asynchronous mode of operation. if during a master reset the asyr input is low, then asynchronous operation of the read port will be selected. during asynchronous operation of the read port the rclk input becomes rd input, this is the asynchronous read strobe input. a rising edge on rd will read data from the fifo via the output register and qn port. ( ren must be tied low during asynchronous operation of the read port). the oe input provides three-state control of the qn output bus, in an asynchronous manner. when the read port is configured for asynchronous operation the device must be operating on idt standard mode, fwft mode is not permissible if the read port is asynchronous. the empty flag ( ef ) operates in an asynchronous manner, that is, the empty flag will be updated based on both a read operation and a write operation. refer to figures 25, 26, 27 and 28 for relevant timing and operational waveforms. retransmit ( rt ) the retransmit operation allows data that has already been read to be accessed again. there are 2 modes of retransmit operation, normal latency and zero latency. there are two stages to retransmit: first, a setup procedure that resets the read pointer to the first location of memory, then the actual retransmit, which consists of reading out the memory contents, starting at the beginning of the memory. retransmit setup is initiated by holding rt low during a rising rclk edge. ren and wen must be high before bringing rt low. when zero latency is utilized, ren does not need to be high before bringing rt low. if idt standard mode is selected, the fifo will mark the beginning of the retransmit setup by setting ef low. the change in level will only be noticeable if ef was high before setup. during this period, the internal read pointer is initialized to the first location of the ram array. when ef goes high, retransmit setup is complete and read operations may begin starting with the first location in memory. since idt standard mode is selected, every word read including the first word following retransmit setup requires a low on ren to enable the rising edge of rclk. see figure 11, retransmit timing (idt standard mode) , for the relevant timing diagram. if fwft mode is selected, the fifo will mark the beginning of the retransmit setup by setting or high. during this period, the internal read pointer is set to the first location of the ram array. when or goes low, retransmit setup is complete; at the same time, the contents of the first location appear on the outputs. since fwft mode is selected, the first word appears on the outputs, no low on ren is necessary. reading all subsequent words requires a low on ren to enable the rising edge of rclk. see figure 12, retransmit timing (fwft mode) , for the relevant timing diagram. in retransmit operation, zero latency mode can be selected using the retransmit mode (rm) pin during a master reset. this can be applied to both idt standard mode and fwft mode. first word fall through/serial in ( fwft/si ) this is a dual purpose pin. during master reset, the state of the fwft/si input determines whether the device will operate in idt standard mode or first word fall through (fwft) mode. if, at the time of master reset, fwft/si is low, then idt standard mode will be selected. this mode uses the empty flag ( ef ) to indicate whether or
20 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 not there are any words present in the fifo memory. it also uses the full flag function ( ff ) to indicate whether or not the fifo memory has any free space for writing. in idt standard mode, every word read from the fifo, including the first, must be requested using the read enable ( ren ) and rclk. if, at the time of master reset, fwft/si is high, then fwft mode will be selected. this mode uses output ready ( or ) to indicate whether or not there is valid data at the data outputs (q n) . it also uses input ready ( ir ) to indicate whether or not the fifo memory has any free space for writing. in the fwft mode, the first word written to an empty fifo goes directly to q n after three rclk rising edges, ren = low is not necessary. subsequent words must be accessed using the read enable ( ren ) and rclk. after master reset, fwft/si acts as a serial input for loading pae and paf offsets into the programmable registers. the serial input function can only be used when the serial loading method has been selected during master reset. serial programming using the fwft/si pin functions the same way in both idt standard and fwft modes. write strobe & write clock (wr/wclk) if synchronous operation of the write port has been selected via asyw , this input behaves as wclk. a write cycle is initiated on the rising edge of the wclk input. data setup and hold times must be met with respect to the low-to-high transition of the wclk. it is permissible to stop the wclk. note that while wclk is idle, the ff / ir , paf and hf flags will not be updated. (note that wclk is only capable of updating hf flag to low). the write and read clocks can either be independent or coincident. if asynchronous operation has been selected this input is wr (write strobe). data is asynchronously written into the fifo via the dn inputs whenever there is a rising edge on wr. in this mode the wen input must be tied low. write enable ( wen ) when the wen input is low, data may be loaded into the fifo ram array on the rising edge of every wclk cycle if the device is not full. data is stored in the ram array sequentially and independently of any ongoing read operation. when wen is high, no new data is written in the ram array on each wclk cycle. to prevent data overflow in the idt standard mode, ff will go low, inhibiting further write operations. upon the completion of a valid read cycle, ff will go high allowing a write to occur. the ff is updated by two wclk cycles + t skew after the rclk cycle. to prevent data overflow in the fwft mode, ir will go high, inhibiting further write operations. upon the completion of a valid read cycle, ir will go low allowing a write to occur. the ir flag is updated by two wclk cycles + t skew after the valid rclk cycle. wen is ignored when the fifo is full in either fwft or idt standard mode. if asynchronous operation of the write port has been selected, then wen must be held active, (tied low). read strobe & read clock (rd/rclk) if synchronous operation of the read port has been selected via asyr , this input behaves as rclk. a read cycle is initiated on the rising edge of the rclk input. data can be read on the outputs, on the rising edge of the rclk input. it is permissible to stop the rclk. note that while rclk is idle, the ef / or , pae and hf flags will not be updated. (note that rclk is only capable of updating the hf flag to high). the write and read clocks can be independent or coincident. if asynchronous operation has been selected this input is rd (read strobe) . data is asynchronously read from the fifo via the output register whenever there is a rising edge on rd. in this mode the ren input must be tied low. the oe input is used to provide asynchronous control of the three- state qn outputs. read enable ( ren ) when read enable is low, data is loaded from the ram array into the output register on the rising edge of every rclk cycle if the device is not empty. when the ren input is high, the output register holds the previous data and no new data is loaded into the output register. the data outputs q 0 -q n maintain the previous data value. in the idt standard mode, every word accessed at q n , including the first word written to an empty fifo, must be requested using ren . when the last word has been read from the fifo, the empty flag ( ef ) will go low, inhibiting further read operations. ren is ignored when the fifo is empty. once a write is performed, ef will go high allowing a read to occur. the ef flag is updated by two rclk cycles + t skew after the valid wclk cycle. in the fwft mode, the first word written to an empty fifo automatically goes to the outputs q n , on the third valid low-to-high transition of rclk + t skew after the first write. ren does not need to be asserted low. in order to access all other words, a read must be executed using ren . the rclk low-to-high transition after the last word has been read from the fifo, output ready ( or ) will go high with a true read (rclk with ren = low), inhibiting further read operations. ren is ignored when the fifo is empty. if asynchronous operation of the read port has been selected, then ren must be held active, (tied low). serial enable ( sen ) the sen input is an enable used only for serial programming of the offset registers. the serial programming method must be selected during master reset. sen is always used in conjunction with ld . when these lines are both low, data at the si input can be loaded into the program register one bit for each low-to-high transition of wclk. when sen is high, the programmable registers retains the previous settings and no offsets are loaded. sen functions the same way in both idt standard and fwft modes. output enable ( oe ) when output enable is enabled (low), the parallel output buffers receive data from the output register. when oe is high, the output data bus (q n ) goes into a high impedance state. load ( ld ) this is a dual purpose pin. during master reset, the state of the ld input, along with fsel0 and fsel1, determines one of eight default offset values for the pae and paf flags, along with the method by which these offset registers can be programmed, parallel or serial (see table 2). after master reset, ld enables write operations to and read operations from the offset registers. only the offset loading method currently selected can be used to write to the registers. offset registers can be read only in parallel. after master reset, the ld pin is used to activate the programming process of the flag offset values pae and paf . pulling ld low will begin a serial loading or parallel load or read of these offset values. bus-matching (bm, iw, ow) the pins bm, iw and ow are used to define the input and output bus widths. during master reset, the state of these pins is used to configure the device bus sizes. see table 1 for control settings. all flags will operate on the word/byte size boundary as defined by the selection of bus width. see figure 4 for bus- matching byte arrangement .
21 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 big-endian/little-endian ( be ) during master reset, a low on be will select big-endian operation. a high on be during master reset will select little-endian format. this function is useful when the following input to output bus widths are implemented: x36 to x18, x36 to x9, x18 to x36 and x9 to x36. if big-endian mode is selected, then the most significant byte (word) of the long word written into the fifo will be read out of the fifo first, followed by the least significant byte. if little-endian format is selected, then the least significant byte of the long word written into the fifo will be read out first, followed by the most significant byte. the mode desired is configured during master reset by the state of the big-endian ( be ) pin. see figure 4 for bus-matching byte arrangement . programmable flag mode (pfm) during master reset, a low on pfm will select asynchronous program- mable flag timing mode. a high on pfm will select synchronous programmable flag timing mode. if asynchronous paf / pae configuration is selected (pfm, low during mrs ), the pae is asserted low on the low-to-high transition of rclk. pae is reset to high on the low-to-high transition of wclk. similarly, the paf is asserted low on the low-to-high transition of wclk and paf is reset to high on the low-to-high transition of rclk. if synchronous pae / paf configuration is selected (pfm, high during mrs) , the pae is asserted and updated on the rising edge of rclk only and not wclk. similarly, paf is asserted and updated on the rising edge of wclk only and not rclk. the mode desired is configured during master reset by the state of the programmable flag mode (pfm) pin. interspersed parity (ip) during master reset, a low on ip will select non-interspersed parity mode. a high will select interspersed parity mode. the ip bit function allows the user to select the parity bit in the word loaded into the parallel port (d 0 -dn) when programming the flag offsets. if interspersed parity mode is selected, then the fifo will assume that the parity bits are located in bit position d 8 , d 17 , d 26 and d 35 during the parallel programming of the flag offsets. if non-interspersed parity mode is selected, then d 8 , d 17 and d 28 are is assumed to be valid bits and d 32 , d 33 , d 34 and d 35 are ignored. ip mode is selected during master reset by the state of the ip input pin. interspersed parity control only has an effect during parallel programming of the offset registers. it does not effect the data written to and read from the fifo. outputs: full flag ( ff / ir ) this is a dual purpose pin. in idt standard mode, the full flag ( ff ) function is selected. when the fifo is full, ff will go low, inhibiting further write operations. when ff is high, the fifo is not full. if no reads are performed after a reset (either mrs or prs ), ff will go low after d writes to the fifo (d = 1,024 for the idt72v3640, 2,048 for the idt72v3650, 4,096 for the idt72v3660, 8,192 for the idt72v3670, 16,384 for the idt72v3680 and 32,768 for the idt72v3690. see figure 7, write cycle and full flag timing (idt standard mode) , for the relevant timing information. in fwft mode, the input ready ( ir ) function is selected. ir goes low when memory space is available for writing in data. when there is no longer any free space left, ir goes high, inhibiting further write operations. if no reads are performed after a reset (either mrs or prs ), ir will go high after d writes to the fifo (d = 1,025 for the idt72v3640, 2,049 for the idt72v3650, 4,097 for the idt72v3660, 8,193 for the idt72v3670, 16,385 for the idt72v3680 and 32,769 for the idt72v3690. see figure 9, write timing (fwft mode) , for the relevant timing information. the ir status not only measures the contents of the fifo memory, but also counts the presence of a word in the output register. thus, in fwft mode, the total number of writes necessary to deassert ir is one greater than needed to assert ff in idt standard mode. ff / ir is synchronous and updated on the rising edge of wclk. ff / ir are double register-buffered outputs. empty flag ( ef / or ) this is a dual purpose pin. in the idt standard mode, the empty flag ( ef ) function is selected. when the fifo is empty, ef will go low, inhibiting further read operations. when ef is high, the fifo is not empty. see figure 8, read cycle, empty flag and first word latency timing (idt standard mode) , for the relevant timing information. in fwft mode, the output ready ( or ) function is selected. or goes low at the same time that the first word written to an empty fifo appears valid on the outputs. or stays low after the rclk low to high transition that shifts the last word from the fifo memory to the outputs. or goes high only with a true read (rclk with ren = low). the previous data stays at the outputs, indicating the last word was read. further data reads are inhibited until or goes low again. see figure 10, read timing (fwft mode) , for the relevant timing information. ef / or is synchronous and updated on the rising edge of rclk. in idt standard mode, ef is a double register-buffered output. in fwft mode, or is a triple register-buffered output. programmable almost-full flag ( paf ) the programmable almost-full flag ( paf ) will go low when the fifo reaches the almost-full condition. in idt standard mode, if no reads are performed after reset ( mrs ), paf will go low after (d - m) words are written to the fifo. the paf will go low after (1,024-m) writes for the idt72v3640, (2,048-m) writes for the idt72v3650, (4,096-m) writes for the idt72v3660, (8,192-m) writes for the idt72v3670, (16,384-m) writes for the idt72v3680 and (32,768-m) writes for the idt72v3690. the offset ?m? is the full offset value. the default setting for this value is stated in the footnote of table 1. in fwft mode, the paf will go low after (1,025-m) writes for the idt72v3640, (2,049-m) writes for the idt72v3650, (4,097-m) writes for the idt72v3660 and (8,193-m) writes for the idt72v3670, (16,385-m) writes for the idt72v3680 and (32,769-m) writes for the idt72v3690, where m is the full offset value. the default setting for this value is stated in table 2. see figure 18, synchronous programmable almost-full flag timing (idt standard and fwft mode) , for the relevant timing information. if asynchronous paf configuration is selected, the paf is asserted low on the low-to-high transition of the write clock (wclk). paf is reset to high on the low-to-high transition of the read clock (rclk). if synchronous paf configuration is selected, the paf is updated on the rising edge of wclk. see figure 20, asynchronous almost-full flag timing (idt standard and fwft mode) . programmable almost-empty flag ( pae ) the programmable almost-empty flag ( pae ) will go low when the fifo reaches the almost-empty condition. in idt standard mode, pae will go low when there are n words or less in the fifo. the offset ?n? is the empty offset value. the default setting for this value is stated in the footnote of table 1. in fwft mode, the pae will go low when there are n+1 words or less in the fifo. the default setting for this value is stated in table 2. see figure 19, synchronous programmable almost-empty flag timing (idt standard and fwft mode) , for the relevant timing information.
22 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 if asynchronous pae configuration is selected, the pae is asserted low on the low-to-high transition of the read clock (rclk). pae is reset to high on the low-to-high transition of the write clock (wclk). if synchronous pae configuration is selected, the pae is updated on the rising edge of rclk. see figure 21, asynchronous programmable almost-empty flag timing (idt standard and fwft mode) . half-full flag ( hf ) this output indicates a half-full fifo. the rising wclk edge that fills the fifo beyond half-full sets hf low. the flag remains low until the difference between the write and read pointers becomes less than or equal to half of the total depth of the device; the rising rclk edge that accomplishes this condition sets hf high. in idt standard mode, if no reads are performed after reset ( mrs or prs ), hf will go low after (d/2 + 1) writes to the fifo, where d = 1,024 for the idt72v3640, 2,048 for the idt72v3650, 4,096 for the idt72v3660, 8,192 for the idt72v3670, 16,384 for the idt72v3680 and 32,768 for the idt72v3690. in fwft mode, if no reads are performed after reset ( mrs or prs ), hf will go low after (d-1/2 + 2) writes to the fifo, where d = 1,025 for the idt72v3640, 2,049 for the idt72v3650, 4,097 for the idt72v3660, 8,193 for the idt72v3670, 16,385 for the idt72v3680 and 32,769 for the idt72v3690. see figure 22, half-full flag timing (idt standard and fwft modes) , for the relevant timing information. because hf is updated by both rclk and wclk, it is considered asynchronous. data outputs (q 0 -q n ) (q 0 -q 35 ) are data outputs for 36-bit wide data, (q 0 - q 17 ) are data outputs for 18-bit wide data or (q 0 -q 8 ) are data outputs for 9-bit wide data.
23 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 d35-d27 d26-d18 d17-d9 d8-d0 a a a d a c b b b c b d c c c a d d d b (a) x36 input to x36 output (b) x36 input to x18 output - big-endian (c) x36 input to x18 output - little-endian (d) x36 input to x9 output - big-endian write to fifo read from fifo 1st: read from fifo b e bm iw ow byte order on input port: 2nd: read from fifo 3rd: read from fifo 4th: read from fifo 1st: read from fifo 1st: read from fifo 2nd: read from fifo 2nd: read from fifo d c (e) x36 input to x9 output - little-endian 1st: read from fifo a b 2nd: read from fifo 3rd: read from fifo 4th: read from fifo 4667 drw08 byte order on output port: l h l l h h l l l h l h h h l h x l l l b e bm iw ow b e bm iw ow b e bm iw ow b e bm iw ow q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 figure 4. bus-matching byte arrangement
24 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 q35-q27 q26-q18 q17-q9 q8-q0 a a d a c b b c b d c d d35-d27 d26-d18 d17-d9 d8-d0 (a) x18 input to x36 output - big-endian read from fifo 1st: write to fifo byte order on input port: 2nd: write to fifo 3rd: write to fifo 4th: write to fifo d35-d27 d26-d18 d17-d9 d8-d0 1st: write to fifo 2nd: write to fifo 4667 drw09 byte order on output port: q35-q27 q26-q18 q17-q9 q8-q0 c d a b (b) x18 input to x36 output - little-endian read from fifo b e bm iw ow h h h l byte order on input port: abcd (a) x9 input to x36 output - big-endian read from fifo b e bm iw ow l h h h byte order on output port: d c b a (b) x9 input to x36 output - little-endian read from fifo b e bm iw ow h h h h b e bm iw ow l h h l d35-d27 d26-d18 d17-d9 d8-d0 d35-d27 d26-d18 d17-d9 d8-d0 d35-d27 d26-d18 d17-d9 d8-d0 d35-d27 d26-d18 d17-d9 d8-d0 q35-q27 q26-q18 q17-q9 q8-q0 q35-q27 q26-q18 q17-q9 q8-q0 figure 4. bus-matching byte arrangement (continued)
25 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 figure 5. master reset timing 4667 drw10 fsel0, fsel1 rt sen t rsf t rsf oe = high oe = low pae paf , hf q 0 - q n t rsf ef / or ff / ir t rsf t rsf if fwft = high, or = high if fwft = low, ef = low if fwft = low, ff = high if fwft = high, ir = low t rss t rss t rss bm, ow, iw be rm pfm ip t rss t rss t rss t rss t rss asyw , asyr t rss mrs t rsr ren t rss fwft/si t rsr t rsr wen t rss ld t rsr t rss t rss t rs
26 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 figure 6. partial reset timing t rs prs t rsr ren t rss 4667 drw11 t rsr wen rt sen t rsf t rsf oe = high oe = low pae paf , hf q 0 - q n t rsf ef / or ff / ir t rsf t rsf if fwft = high, or = high if fwft = low, ef = low if fwft = low, ff = high if fwft = high, ir = low t rss t rss t rss
27 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 figure 8. read cycle, empty flag and first data word latency timing (idt standard mode) notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high (after one rclk cycle plus t ref ). if the time between the rising edge of wclk and the rising edge of rclk is less than t skew1 , then ef deassertion may be delayed one extra rclk cycle. 2. ld = high. 3. first data word latency = t skew1 + 1*t rclk + t ref. notes: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high (after one wclk cycle pus t wff ). if the time between the rising edge of the rclk and the rising edge of the wclk is less than t skew1 , then the ff deassertion may be delayed one extra wclk cycle. 2. ld = high, oe = low, ef = high figure 7. write cycle and full flag timing (idt standard mode) no operation rclk ren 4667 drw13 ef t clk t clkh t clkl t enh t ref t a t olz t oe q0 - qn oe wclk (1) t skew1 wen d0 - dn t ens t ens t enh t ds t dh d 0 1 2 t olz no operation last word d 0 d 1 d 1 t ens t enh t ds t dh t ohz last word t ref t enh t ens t a t a t ref t ens t enh d 0 - d n wen rclk ren t enh t enh q 0 - q n data read next data read data in output register t skew1 (1) 4667 drw12 wclk no write 1 2 1 2 t ds no write t wff t wff t wff t a t ens t ens t skew1 (1) t ds t a d x t dh t clk t clkh t clkl d x +1 t wff t dh ff
28 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 figure 9. write timing (first word fall through mode) notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that or will go low after two rclk cycles plus t ref . if the time between the rising edge of wclk and the rising edge of rclk is less than t skew1 , then or assertion may be delayed one extra rclk cycle. 2. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that pae will go high after one rclk cycle plus t paes . if the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then the pae deassertion may be delayed one extra rclk cycle. 3. ld = high, oe = low 4. n = pae offset, m = paf offset and d = maximum fifo depth. 5. d = 1,025 for idt72v3640, 2,049 for idt72v3650, 4,097 for idt72v3660, 8,193 for idt72v3670, 16,385 for the idt72v3680 and 32,769 for the idt72v3690. 6. first data word latency = t skew1 + 2*t rclk + t ref. w 1 w 2 w 4 w [n +2] w [d-m-1] w [d-m-2] w [d-1] w d w [n+3] w [n+4] w [d-m] w [d-m+1] wclk wen d 0 - d 17 rclk t dh t ds t skew1 (1) ren q 0 - q 17 paf hf pae ir t ds t ds t ds t skew2 t a t ref or t paes t hf t pafs t wff w [d-m+2] w 1 t enh 4667 drw14 data in output register (2) w 3 1 2 3 1 d-1 2 +1 ] [ w d-1 +2 ] [ w 2 d-1 +3 ] [ w 2 1 2 t ens
29 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 figure 10. read timing (first word fall through mode) notes: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ir will go low after one wclk cycle plus t wff . if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then the ir assertion may be delayed one extra wclk cycle. 2. t skew2 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that paf will go high after one wclk cycle plus t pafs . if the time between the rising edge of rclk and the rising edge of wclk is less than t skew2 , then the paf deassertion may be delayed one extra wclk cycle. 3. ld = high 4. n = pae offset, m = paf offset and d = maximum fifo depth. 5. d = 1,025 for idt72v3640, 2,049 for idt72v3650, 4,097 for idt72v3660, 8,193 for idt72v3670, 16,385 for the idt72v3680 and 32, 769 for the idt72v3690. wclk 12 wen d 0 - d 17 rclk t ens ren q 0 - q 17 paf hf pae ir or w 1 w 1 w 2 w 3 w m+2 w [m+3] t ohz t skew1 t enh t ds t dh t oe t a t a t a t pafs t wff t wff t ens oe t skew2 w d 4667 drw15 t paes w [d-n] w [d-n-1] t a t a t hf t ref w [d-1] w d t a w [d-n+1] w [m+4] w [d-n+2] (1) (2) t ens d-1 + 1 ] [ w 2 d-1 + 2 ] [ w 2 1
30 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 notes: 1. retransmit setup is complete after ef returns high, only then can a read operation begin. 2. oe = low. 3. w 1 = first word written to the fifo after master reset, w 2 = second word written to the fifo after master reset. 4. no more than d - 2 may be written to the fifo between reset (master or partial) and retransmit setup. therefore, ff will be high throughout the retransmit setup procedure. d = 1,024 for idt72v3640, 2,048 for idt72v3650, 4,096 for idt72v3660, 8,192 for idt72v3670, 16,384 for the idt72v3680 and 32,76 8 for the idt72v3690. 5. there must be at least two words written to the fifo before a retransmit operation can be invoked. 6. rm is set high during mrs. figure 11. retransmit timing (idt standard mode) t ref t rts t enh 4667 drw16 t a t ens w x wclk rclk ren rt ef paf hf pae q 0 - q n t skew2 12 1 w 1 t pafs t hf t paes t ref w x+1 2 w 2 t enh wen t ens t rts t ens t enh (3) t a t a (3)
31 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 notes: 1. retransmit setup is complete after or returns low. 2. no more than d - 2 words may be written to the fifo between reset (master or partial) and retransmit setup. therefore, ir will be low throughout the retransmit setup procedure. d = 1,025 for the idt72v3640, 2,049 for the idt72v3650, 4,097 for the idt72v3660, 8,193 for the idt72v3670, 16,385 for the idt7 2v3680 and 32,769 for the idt72v3690. 3. oe = low. 4. w 1 , w 2 , w 3 = first, second and third words written to the fifo after master reset. 5. there must be at least two words written to the fifo before a retransmit operation can be invoked. 6. rm is set high during mrs. figure 12. retransmit timing (fwft mode) t ref t rts t enh 4667 drw17 t ens w x wclk rclk ren rt or paf hf pae q 0 - q n t skew2 12 1 t pafs t hf t paes t ref w x+1 2 w 2 t enh t rts wen t ens w 1 t ens (4) 3 4 t enh w 3 t a t a t a w 4 t a (4) (4)
32 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 notes: 1. if the part is empty at the point of retransmit, the empty flag ( ef ) will be updated based on rclk (retransmit clock cycle), valid data will also appear on the output. 2. oe = low. 3. w 1 = first word written to the fifo after master reset, w 2 = second word written to the fifo after master reset. 4. no more than d - 2 may be written to the fifo between reset (master or partial) and retransmit setup. therefore, ff will be high throughout the retransmit setup procedure. d = 1,024 for idt72v3640, 2,048 for idt72v3650, 4,096 for idt72v3660, 8,192 for idt72v3670, 16,384 for the idt72v3680 and 32,76 8 for the idt72v3690. 5. there must be at least two words written to the fifo before a retransmit operation can be invoked. 6. rm is set low during mrs. figure 13. zero latency retransmit timing (idt standard mode) t rts t enh 4667 drw18 t a t ens w x wclk rclk ren rt ef paf hf pae q 0 - q n t skew2 12 1 w 3 (3) t pafs t hf t paes w x+1 2 w 4 wen t ens t enh t a t a 3 t a t a w 1 (3) w 2 (3)
33 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 figure 15. serial loading of programmable flag registers (idt standard and fwft modes) note: 1. x = 9 for the idt72v3640, x = 10 for the idt72v3650, x = 11 for the idt72v3660, x = 12 for the idt72v3670, x = 13 for the idt 72v3680 and x = 14 for the idt72v3690. notes: 1. if the part is empty at the point of retransmit, the output ready flag ( or ) will be updated based on rclk (retransmit clock cycle), valid data will also appear on the output. 2. no more than d - 2 words may be written to the fifo between reset (master or partial) and retransmit setup. therefore, ir will be low throughout the retransmit setup procedure. d = 1,025 for the idt72v3640, 2,049 for the idt72v3650, 4,097 for the idt72v3660, 8,193 for the idt72v3670, 16,385 for the idt7 2v3680 and 32,769 for the idt72v3690. 3. oe = low. 4. w 1 , w 2 , w 3 = first, second and third words written to the fifo after master reset. 5. there must be at least two words written to the fifo before a retransmit operation can be invoked. 6. rm is set low during mrs. figure 14. zero latency retransmit timing (fwft mode) wclk sen si 4667 drw20 t enh t ens t lds ld t ds bit 0 empty offset bit x bit 0 full offset (1) t enh bit x (1) t ldh t dh t ldh t rts t enh 4667 drw19 t ens w x wclk rclk ren rt or paf hf pae q 0 - q n t skew2 12 1 t pafs t hf t paes w x+1 2 w 3 wen t ens w 2 (4) 4 5 t enh w 4 t a t a t a w 5 t a (4) (4) 3 t a w1
34 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 notes: 1. m = paf offset. 2. d = maximum fifo depth. in idt standard mode: d = 1,024 for the idt72v3640, 2,048 for the idt72v3650, 4,096 for the idt72v3660 and 8,192 for the idt72v 3670, 16,384 for the idt72v3680 and 32,768 for the idt72v3690. in fwft mode: d = 1,025 for the idt72v3640, 2,049 for the idt72v3650, 4,097 for the idt72v3660, 8,193 for the idt72v3670, 16,3 85 for the idt72v3680 and 32,769 for the idt72v3690. 3. t skew2 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that paf will go high (after one wclk cycle plus t pafs ). if the time between the rising edge of rclk and the rising edge of wclk is less than t skew2 , then the paf deassertion time may be delayed one extra wclk cycle. 4. paf is asserted and updated on the rising edge of wclk only. 5. select this mode by setting pfm high during master reset. wclk wen paf rclk (3) t pafs ren 4667 drw23 d - (m+1) words in fifo (2) d - m words in fifo (2) 1 2 12 d-(m+1) words in fifo (2) t pafs t enh t ens t skew2 t enh t ens t clkl t clkl rclk ld ren q 0 - q n t ldh t lds t ens data in output register pae offset paf offset t enh t enh t ldh 4667 drw22 t clk t a t a t clkh t clkl wclk ld wen d 0 - d n 4667 drw21 t lds t ens pae offset paf offset t ds t dh t ldh t enh t clk t ldh t enh t dh t clkh t clkl figure 18. synchronous programmable almost-full flag timing (idt standard and fwft modes) notes: 1. oe = low. 2. the timing diagram illustrates reading of offset registers with an output bus width of 36 bits. figure 17. parallel read of programmable flag registers (idt standard and fwft modes) figure 16. parallel loading of programmable flag registers (idt standard and fwft modes) note: 1. this timing diagram illustrates programming with an input bus width of 36 bits.
35 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 notes: 1. n = pae offset. 2. for idt standard mode 3. for fwft mode. 4. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that pae will go high (after one rclk cycle plus t paes ). if the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then the pae deassertion may be delayed one extra rclk cycle. 5. pae is asserted and updated on the rising edge of wclk only. 6. select this mode by setting pfm high during master reset. figure 19. synchronous programmable almost-empty flag timing (idt standard and fwft modes) notes: 1. m = paf offset. 2. d = maximum fifo depth. in idt standard mode: d = 1,024 for the idt72v3640, 2,048 for the idt72v3650, 4,096 for the idt72v3660, 8,192 for the idt72v3670, 16,384 for the idt7 2v3680 and 32,768 for the idt72v3690. in fwft mode: d = 1,025 for the idt72v3640, 2,049 for the idt72v3650, 4,097 for the idt72v3660, 8,193 for the idt72v3670, 16,38 5 for the idt72v3680 and 32,769 for the idt72v3690. 3. paf is asserted to low on wclk transition and reset to high on rclk transition. 4. select this mode by setting pfm low during master reset. figure 20. asynchronous programmable almost-full flag timing (idt standard and fwft modes) wclk t clkh t clkl t ens t enh wen paf t ens t pafa d - (m + 1) words in fifo rclk t pafa ren 4667 drw25 d - m words in fifo d - (m + 1) words in fifo wclk t enh t clkh t clkl wen pae rclk t ens n words in fifo (2) , n+1 words in fifo (3) t paes t skew2 t paes 12 12 (4) ren 4667 drw24 t ens t enh n+1 words in fifo (2) , n+2 words in fifo (3) n words in fifo (2) , n+1 words in fifo (3)
36 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 notes: 1. n = pae offset. 2. for idt standard mode. 3. for fwft mode. 4. pae is asserted low on rclk transition and reset to high on wclk transition. 5. select this mode by setting pfm low during master reset. notes: 1. in idt standard mode: d = maximum fifo depth. d = 1,024 for the idt72v3640, 2,048 for the idt72v3650, 4,096 for the idt72v366 0, 8,192 for the idt72v3670, 16,384 for the idt72v3680 and 32,768 for the idt72v3690. 2. in fwft mode: d = maximum fifo depth. d = 1,025 for the idt72v3640, 2,049 for the idt72v3650, 4,097 for the idt72v3660, 8,1 93 for the idt72v3670, 16,385 for the idt72v3680 and 32,769 for the idt72v3690. figure 22. half-full flag timing (idt standard and fwft modes) figure 21. asynchronous programmable almost-empty flag timing (idt standard and fwft modes) wclk t ens t enh wen hf t ens t hf rclk t hf ren 4667 drw27 t clkl t clkh d/2 words in fifo (1) , [ + 1 ] words in fifo (2) d-1 2 d/2 + 1 words in fifo (1) , [ + 2 ] words in fifo (2) d/2 words in fifo (1) , [ + 1 ] words in fifo (2) d-1 2 d-1 2 wclk t clkh t clkl t ens t enh wen pae t ens t paea n + 1 words in fifo (2) , n + 2 words in fifo (3) n words in fifo (2) , n + 1 words in fifo (3) rclk t paea ren 4667 drw26 n words in fifo (2) , n + 1 words in fifo (3)
37 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 figure 23. asynchronous write, synchronous read, full flag operation (idt standard mode) figure 24. asynchronous write, synchronous read, empty flag operation (idt standard mode) note: 1. oe = low and wen = low. note: 1. oe = low and wen = low. rclk ren 4667 drw28 ff qn w 0 t a w 1 t enh t ens t ffa t ffa t ffa wr t cyh dn t ds w d t dh w d+1 t cyc rclk ren 4667 drw29 qn last word t a w 0 t enh t ens t skew wr dn w 0 t dh 1 2 t a w 1 t ref t ref ef t cyl t ds t cyh w 1 t dh t ds t cyc
38 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 figure 25. synchronous write, asynchronous read, full flag operation (idt standard mode) figure 26. synchronous write, asynchronous read, empty flag operation (idt standard mode) note: 1. oe = low and ren = low. 2. asynchronous read is available in idt standard mode only. note: 1. oe = low and ren = low. 2. asynchronous read is available in idt standard mode only. wclk wen 4667 drw30 qn t skew rd dn d f 1 2 t wff t wff ff t cyl t cyh last word no write d f+1 t aa w x t aa w x+1 t cyc wclk wen 4667 drw31 qn last word in output register w 0 rd dn t efa ef t cyh t ens t enh w 0 t ds t dh t efa t aa t rpe
39 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 figure 27. asynchronous write, asynchronous read, empty flag operation (idt standard mode) figure 28. asynchronous write, asynchronous read, full flag operation (idt standard mode) notes: 1. oe = low, wen = low, and ren = low. 2. asynchronous read is available in idt standard mode only. notes: 1. oe = low, wen = low, and ren = low. 2. asynchronous read is available in idt standard mode only. 4667 drw32 qn last word in o/p register t aa w 0 t cyh wr dn w 0 t dh t aa w 1 t efa t efa ef t cyl w 1 t dh t ds rd t cyc t rpe 4667 drw33 t cyh wr dn w y t dh t ffa ff t cyl t ds w y+1 t dh t ds rd w x t aa w x+1 w x+2 qn t ffa t cyc t cyh t cyl t cyc t aa
40 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 notes: 1. use an and gate in idt standard mode, an or gate in fwft mode. 2. do not connect any output control signals directly together. 3. fifo #1 and fifo #2 must be the same depth, but may be different word widths. optional configurations width expansion configuration word width may be increased simply by connecting together the control signals of multiple devices. status flags can be detected from any one device. the exceptions are the ef and ff functions in idt standard mode and the ir and or functions in fwft mode. because of variations in skew between rclk and wclk, it is possible for ef / ff deassertion and ir / or assertion to vary by one cycle between fifos. in idt standard mode, such problems can be figure 29. block diagram of 1,024 x 72, 2,048 x 72, 4,096 x 72, 8,192 x 72, 16,384 x 72 and 32,768 x 72 width expansion avoided by creating composite flags, that is, anding ef of every fifo, and separately anding ff of every fifo. in fwft mode, composite flags can be created by oring or of every fifo, and separately oring ir of every fifo. figure 29 demonstrates a width expansion using two idt72v3640/ 72v3650/72v3660/72v3670/72v3680/72v3690 devices. d 0 - d 35 from each device form a 72-bit wide input bus and q 0 -q 35 from each device form a 72- bit wide output bus. any word width can be attained by adding additional idt72v3640/72v3650/72v3660/72v3670/72v3680/72v3690 devices. write clock (wclk) m + n m n master reset ( mrs ) read clock (rclk) data out n m + n write enable ( wen ) full flag/input ready ( ff / ir ) programmable ( paf ) programmable ( pae ) empty flag/output ready ( ef / or ) #2 output enable ( oe ) read enable ( ren ) m load ( ld ) idt 72v3640 72v3650 72v3660 72v3670 72v3680 72v3690 empty flag/output ready ( ef / or ) #1 partial reset ( prs ) 4667 drw34 full flag/input ready ( ff / ir ) #2 half-full flag ( hf ) first word fall through/ serial input (fwft/si) retransmit ( rt ) #1 fifo #2 gate (1) gate (1) d 0 - dm data in dm +1 - dn q 0 - qm qm +1 - qn fifo #1 idt 72v3640 72v3650 72v3660 72v3670 72v3680 72v3690
41 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 figure 30. block diagram of 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36 and 65,536 x 36 depth expansion depth expansion configuration (fwft mode only) the idt72v3640 can easily be adapted to applications requiring depths greater than 1,024, 2,048 for the idt72v3650, 4,096 for the idt72v3660, 8,192 for the idt72v3670, 16,384 for the idt72v3680 and 32,768 for the idt72v3690 with an 36-bit bus width. in fwft mode, the fifos can be connected in series (the data outputs of one fifo connected to the data inputs of the next) with no external logic necessary. the resulting configuration provides a total depth equivalent to the sum of the depths associated with each single fifo. figure 30 shows a depth expansion using two idt72v3640/ 72v3650/72v3660/72v3670/72v3680/72v3690 devices. care should be taken to select fwft mode during master reset for all fifos in the depth expansion configuration. the first word written to an empty configuration will pass from one fifo to the next ("ripple down") until it finally appears at the outputs of the last fifo in the chain ? no read operation is necessary but the rclk of each fifo must be free-running. each time the data word appears at the outputs of one fifo, that device's or line goes low, enabling a write to the next fifo in line. for an empty expansion configuration, the amount of time it takes for or of the last fifo in the chain to go low (i.e. valid data to appear on the last fifo's outputs) after a word has been written to the first fifo is the sum of the delays for each individual fifo: (n ? 1)*(4*transfer clock) + 3*t rclk where n is the number of fifos in the expansion and t rclk is the rclk period. note that extra cycles should be added for the possibility that the t skew1 specification is not met between wclk and transfer clock, or rclk and transfer clock, for the or flag. the "ripple down" delay is only noticeable for the first word written to an empty depth expansion configuration. there will be no delay evident for subsequent words written to the configuration. the first free location created by reading from a full depth expansion configuration will "bubble up" from the last fifo to the previous one until it finally moves into the first fifo of the chain. each time a free location is created in one fifo of the chain, that fifo's ir line goes low, enabling the preceding fifo to write a word to fill it. for a full expansion configuration, the amount of time it takes for ir of the first fifo in the chain to go low after a word has been read from the last fifo is the sum of the delays for each individual fifo: (n ? 1)*(3*transfer clock) + 2 t wclk where n is the number of fifos in the expansion and t wclk is the wclk period. note that extra cycles should be added for the possibility that the t skew1 specification is not met between rclk and transfer clock, or wclk and transfer clock, for the ir flag. the transfer clock line should be tied to either wclk or rclk, whichever is faster. both these actions result in data moving, as quickly as possible, to the end of the chain and free locations to the beginning of the chain. dn input ready write enable write clock wen wclk ir data in rclk read clock rclk ren oe output enable output ready qn dn ir gnd wen wclk or ren oe qn read enable or data out idt 72v3640 72v3650 72v3660 72v3670 72v3680 72v3690 transfer clock 4667 drw 35 n n n fwft/si fwft/si fwft/si idt 72v3640 72v3650 72v3660 72v3670 72v3680 72v3690
42 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 figure 31. standard jtag timing system interface parameters parameter symbol test conditions min. max. units jtag clock input period t tck - 100 - ns jtag clock high t tckhigh -40-ns jtag clock low t tcklow -40-ns jtag clock rise time t tckrise --5 (1) ns jtag clock fall time t tckfall --5 (1) ns jtag reset t rst -50-ns jtag reset recovery t rsr -50-ns jtag ac electrical characteristics (v cc = 3.3v 5%; tcase = 0 c to +85 c) idt72v3640 idt72v3650 idt72v3660 idt72v3670 idt72v3680 idt72v3690 parameter symbol test conditions min. max. units data output t do = max - 20 ns data output hold t doh (1) 0-ns data input t ds t rise=3ns 10 - ns t dh t fall=3ns 10 - note: 1. 50pf loading on external output signals. note: 1. guaranteed by design. t tck t 4 t 2 t 3 t 1 t ds t dh tdo tdo tdi/ tms tck trst t 5 t do notes to diagram: t1 = t tcklow t2 = t tckhigh t3 = t tckfall t4 = t tckrise t5 = t rst (reset pulse width) t6 = t rsr (reset recovery) 4667 drw36 t 6
43 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 jtag interface five additional pins (tdi, tdo, tms, tck and trst ) are provided to support the jtag boundary scan interface. the idt72v3640/72v3650/ 72v3660/72v3670/72v3680/72v3690 incorporates the necessary tap con- troller and modified pad cells to implement the jtag facility. note that idt provides appropriate boundary scan description language program files for these devices. the standard jtag interface consists of four basic elements: ? test access port (tap) ? tap controller ? instruction register (ir) ? data register port (dr) the following sections provide a brief description of each element. for a complete description refer to the ieee standard test access port specification (ieee std. 1149.1-1990). the figure below shows the standard boundary-scan architecture figure 32. boundary scan architecture test access port (tap) the tap interface is a general-purpose port that provides access to the internal of the processor. it consists of four input ports (tclk, tms, tdi, trst ) and one output port (tdo). the tap controller the tap controller is a synchronous finite state machine that responds to tms and tclk signals to generate clock and control signals to the instruction and data registers for capture and update of data. t a p tap cont- roller mux deviceid reg. boundary scan reg. bypass reg. clkdr, shiftdr updatedr tdo tdi tms tclk trst clklr, shiftlr updatelr instruction register instruction decode control signals 4667 drw37
44 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 figure 33. tap controller state diagram test-logic reset run-test/ idle 1 0 0 select- dr-scan select- ir-scan 1 1 1 capture-ir 0 capture-dr 0 0 exit1-dr 1 pause-dr 0 exit2-dr 1 update-dr 1 exit1-ir 1 exit2-ir 1 update-ir 1 1 0 1 1 1 4667 drw38 0 shift-dr 0 0 0 shift-ir 0 0 pause-ir 0 1 input = tms 0 0 1 refer to the ieee standard test access port specification (ieee std. 1149.1) for the full state diagram all state transitions within the tap controller occur at the rising edge of the tclk pulse. the tms signal level (0 or 1) determines the state progression that occurs on each tclk rising edge. the tap controller takes precedence over the fifo memory and must be reset after power up of the device. see trst description for more details on tap controller reset. capture-dr data is loaded from the parallel input pins or core outputs into the data register. shift-dr the previously captured data is shifted in serially, lsb first at the rising edge of tclk in the tdi/tdo path and shifted out serially, lsb first at the falling edge of tclk towards the output. update-dr the shifting process has been completed. the data is latched into their parallel outputs in this state to be accessed through the internal bus. exit1-dr / exit2-dr this is a temporary controller state. if tms is held high, a rising edge applied to tck while in this state causes the controller to enter the update-dr state. this terminates the scanning process. all test data registers selected by the current instruction retain their previous state unchanged. pause-dr this controller state allows shifting of the test data register in the serial path between tdi and tdo to be temporarily halted. all test data registers selected by the current instruction retain their previous state unchanged. capture-ir, shift-ir and update-ir, exit-ir and pause-ir are similar to data registers. these instructions operate on the instruction registers. notes: 1. five consecutive tck cycles with tms = 1 will reset the tap. 2. tap controller does not automatically reset upon power-up. the user must provide a reset to the tap controller (either by trst or tms). 3. tap controller must be reset before normal fifo operations can begin.
45 commercial and industrial temperature ranges idt72v3640/50/60/70/80/90 3.3v high density supersync ii tm 36-bit fifo 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 the instruction register the instruction register allows an instruction to be shifted in serially into the processor at the rising edge of tclk. the instruction is used to select the test to be performed, or the test data register to be accessed, or both. the instruction shifted into the register is latched at the completion of the shifting process when the tap controller is at update- ir state. the instruction register must contain 4 bit instruction register-based cells which can hold instruction data. these mandatory cells are located nearest the serial outputs they are the least significant bits. test data register the test data register contains three test data registers: the bypass, the boundary scan register and device id register. these registers are connected in parallel between a common serial input and a common serial data output. the following sections provide a brief description of each element. for a complete description, refer to the ieee standard test access port specification (ieee std. 1149.1-1990). test bypass register the register is used to allow test data to flow through the device from tdi to tdo. it contains a single stage shift register for a minimum length in serial path. when the bypass register is selected by an instruction, the shift register stage is set to a logic zero on the rising edge of tclk when the tap controller is in the capture-dr state. the operation of the bypass register should not have any effect on the operation of the device in response to the bypass instruction. the boundary-scan register the boundary scan register allows serial data tdi be loaded in to or read out of the processor input/output ports. the boundary scan register is a part of the ieee 1149.1-1990 standard jtag implementation. the device identification register the device identification register is a read only 32-bit register used to specify the manufacturer, part number and version of the processor to be determined through the tap in response to the idcode instruction. idt jedec id number is 0xb3. this translates to 0x33 when the parity is dropped in the 11-bit manufacturer id field. for the idt72v3640/72v3650/72v3660/72v3670/72v3680/72v3690, the part number field contains the following values: idt72v3640/50/60/70/80/90 jtag device identification register 31(msb) 28 27 12 11 1 0(lsb) version (4 bits) part number (16-bit) manufacturer id (11-bit) 0x0 0x33 1 jtag instruction register the instruction register allows instruction to be serially input into the device when the tap controller is in the shift-ir state. the instruction is decoded to perform the following: ? select test data registers that may operate while the instruction is current. the other test data registers should not interfere with chip operation and the selected data register. ? define the serial test data register path that is used to shift data between tdi and tdo during data register scanning. the instruction register is a 4 bit field (i.e.ir3, ir2, ir1, ir0) to decode 16 different possible instructions. instructions are decoded as follows. hex instruction function value 0x00 extest select boundary scan register 0x02 idcode select chip identification data register 0x01 sample/preload select boundary scan register 0x03 hi-z jtag 0x0f bypass select bypass register table 6. jtag instruction register decoding the following sections provide a brief description of each instruction. for a complete description refer to the ieee standard test access port specification (ieee std. 1149.1-1990). extest the mandatory extest instruction is provided for external circuity and board level interconnection check. idcode this instruction is provided to select device identification register to read out manufacture?s identity, part number and version number. sample/preload the mandatory sample/preload instruction allows data values to be loaded onto the latched parallel outputs of the boundary-scan shift register prior to selection of the boundary-scan test instruction. the sample instruction allows a snapshot of data flowing from the system pins to the on-chip logic or vice versa. high-z this instruction places all the output pins on the device into a high impedance state. bypass the bypass instruction contains a single shift-register stage and is set to provide a minimum-length serial path between the tdi and the tdo pins of the device when no test operation of the device is required. device part# field idt72v3640 04e5 idt72v3650 04e4 idt72v3660 04e3 idt72v3670 04e2 idt72v3680 04e1 idt72v3690 04e0
46 corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1753 santa clara, ca 95054 fax: 408-492-8674 email: fifoh elp@idt.com www.idt.com ordering information thin plastic quad flatpack (tqfp, pk128-1) plastic ball grid array (pbga, bb144-1) commercial (0 c to +70 c) industrial (-40 c to +85 c) low power 1,024 x 36 ? 3.3v supersync ? ii fifo 2,048 x 36 ? 3.3v supersync ? ii fifo 4,096 x 36 ? 3.3v supersync ? ii fifo 8,192 x 36 ? 3.3v supersync ? ii fifo 16,384 x 36 ? 3.3v supersync ? ii fifo 32,768 x 36 ? 3.3v supersync ? ii fifo 4667 drw 39 clock cycle time (t clk ) speed in nanoseconds commercial, pbga & tqfp only commercial, pbga & tqfp only commercial, tqfp only com?l & ind?l, tqfp only 6 7-5 10 15 idt xxxxx device type x power xx speed x package x process / temperature range blank i (1) 72v3640 72v3650 72v3660 72v3670 72v3680 72v3690 pf bb l note: 1. industrial temperature range is available by special order for speed grades faster than 15ns. datasheet document history 05/25/2000 pgs. 1, 6, 7, 8, 34, and 35. 07/28/2000 pgs. 13, 14, and 34. 12/14/2000 pgs. 6, 7, and 8. 03/27/2001 pg. 7. 04/06/2001 pgs. 4, 5, and 18. 12/14/2001 pgs. 1-46. 12/20/2001 pg. 9. 03/25/2002 pg. 42. 04/19/2002 pg. 3. 05/24/2002 pgs. 3, and 11. 01/20/2003 pgs. 1, 7, 9, 10, and 16. 02/11/2003 pgs. 7, and 44. 07/15/2003 pgs. 3, 19, and 37-39. 09/29/2003 pg. 8.

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